1. Field of the Invention
This invention relates to a signal processing circuit and more particularly to a clamping circuit for colors or luminarice.
2. Description of the Related Art
The conventional color or luminance clamping circuit has been arranged to integrate data for a predetermined period (one field period, for example), to obtain a mean value of the data by dividing the integrated data value by the number of the data, to use the mean value as a clamping value, and to apply clamping to an original signal by subtracting the clamping value from the original signal.
One example of the conventional arrangement is described as follows with reference to FIGS. 1 to 3, which relate to the conventional color clamping circuit: FIG. 1 is a circuit diagram showing the conventional color clamping circuit. FIG. 2 is a time chart showing a phase relation obtained among signals shown in FIG. 1. FIG. 3 is a circuit diagram showing the internal arrangement of each of integrators used for the conventional color clamping circuit. In computing the clamping value, the conventional color clamping circuit individually accumulates and adds up each of continuous red (R) data, green (G) data and blue (B) data by latching them respectively in accordance with clock signals CLK1 to CLK3 as shown in FIG. 1. Further, as shown in FIG. 3, the conventional color clamping circuit is provided with adders for each of the data of three color components, including the R, G and B components.
The conventional luminance clamping circuit is described by way of example as follows, with reference to FIGS. 4 to 6: FIG. 4 is a circuit diagram showing one example of the conventional luminance clamping circuit. FIG. 5 is a circuit diagram showing another example of the conventional luminance clamping circuit. FIG. 6 is a time chart showing a phase relation obtained among signals shown in FIGS. 4 and 5. The conventional luminance clamping circuit is arranged to compute the clamping value in the following manner: data of different components are accumulated and added by lines, as shown in FIG. 6. For example, the data of Wr and Gb components are accumulated and added for one line and the data of Gr and Wb components are accumulated and added for another line. The accumulating and adding action is performed by using a main clock signal CLK in the case of FIG. 4 and by using a clock signal CLK2 obtained by frequency-dividing the main clock signal CLK by two in the case of FIG. 5.
The example of the conventional color clamping circuit shown in FIG. 1 operates as follows: in accumulating and adding, for example, the R component, an R component part is assumed to appear in a signal SIG at the rise of a main clock signal MCLK. Then, at the same time, another R component part appears in another input of an adder at the rise of the clock signal CLK1. These R component parts are added up at the adder. This addition must be completed before the main clock signal MCLK comes to rise again. This is because the R, G and B components are continuous data. The G component would appear in the signal SIG during a next period of the clock signal and the R and G components would be added together. Therefore, a different color component tends to be mixed in the data accumulated and added by each integrator. Further, depending on the arrangement of the device, the adding process might not be completed within one clock period. In such a case, it is hardly possible to obtain an accurate clamping value.
The luminance clamping circuit also has presented a problem similar to the problem presented by the color clamping circuit. It is necessary also for a luminance clamping circuit to use a high-frequency clock signal for latching continuous data in accordance with a main clock signal (CLK in FIG. 6). Therefore, depending on the arrangement of the device, an adding process might not be completed within one clock period and thus might fail to give an accurate clamping value. To solve this problem, it has been contrived to use a clock signal obtained by dividing the main clock signal of the system by two, considering the speed of the clock signal, as shown in FIG. 5. In this case, however, the signal components are integrated by latching them by means of a delay device disposed before an adder to integrate only the Wr component for a line n and only the Gr component for a next line n+1 as shown in FIG. 6. This arrangement also has failed to give an accurate luminance clamping value.
Further, the conventional clamping circuit has presented another problem in that the amount of hardware has been increased by the use of three adders which are individually arranged as shown in FIG. 3 to integrate respectively the data of R, G and B color components.